DVI OUTPUT EYE DIAGRAMSOF CH7009A/7301A VS. CH7009B/7301B Technical Bulletin 41

2022-10-20
●CH7009B/7301B, which are the successors of CH7009A/7301A, are fully DDWG compliant DVI transmitters. The new chips are able to transmit DVI display data from 25MHz up to 165 MHz pixel clocks. CH7009A/7301Ais capable of transmitting data from 25 MHz to 135 MHz. A screened version of CH7009A/7301A would be able to support 165 MHz pixel clock if the DVI PLL is powered by 3.6V. This document gives a overall picture of what the DVI output eye-diagrams of CH7009A/7301A and CH7009B/7301B look like. The eye-diagrams of CH7009B/7301B support that these chips are versatile DVI transmitters with full compliance to DDWG specifications

Chrontel

CH7009CH7301CH7009BCH7301BCH7009ACH7301A

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Part#

DVI transmitters

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Application note & Design Guide

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Please see the document for details

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English Chinese Chinese and English Japanese

01/20/2003

Rev. 1.0

TB-41

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