PMIC BD96801 powering Xilinx Spartan-7 FPGA User's Guide
●The evaluation board has been designed to demonstrate the performance of the PMIC BD96801 when powering a Xilinx Spartan-7 FPGA. The BD96801 contains 4 buck converters and 3 LDOs that can be flexibly configured via factory OTP settings, user EEPROM settings or I2C commands.
●The user's guide contains a schematic of the evaluation board, a Bill of Material list (BOM) and also description about the overall functioning of the evaluation board. Additionally, the user's guide contains important notices and warnings that need to be carefully reviewed prior to use of the board.
●Introduction
■Current FPGA-based designs require highly integrated power supply solutions containing multiple well-defined and accurate output voltages. Starting up and shutting down an FPGA demands a well-defined power sequencing. The scalable PMIC BD96801 is a configurable power management IC that can quickly be adapted to work with various FPGAs. The voltages of the PMIC outputs are programmable via OTP setting or I2C. The timing for up- and down-sequencing of the voltage rails can be individually defined as well.
■This manual explains how to use the BD96801-SPA7-EVK-301 with ROHM's PMIC BD96801 in UQFN48FV6060 package.
●Key features
■The evaluation board is an eight layered PCB with dimensions of approximately 120 mm by 100 mm. Figure 1 shows the picture of the EVK, indicating key components onboard. To operate the EVK you need a DC/DC power supply (10V to 24V, > 300mA).
■The heart of the board is the Spartan-7 FPGA. It connects to a 128Mb flash memory device and a 4Gb DDR3L memory IC. It is clocked by an external oscillator.
■The system is powered by a primary buck controller BD9F500, a secondary PMIC BD96801 as well as a termination regulator BD35395. The PMIC has preconfigured OTP settings which defines all required power settings, such as output voltages, protection levels and voltage up- and down-sequencing. If needed, these settings can be adjusted by programming an onboard EEPROM via I2C interface. If the EEPROM is not empty, the PMIC is initialized with its content during start-up.
■The programmable flash memory transfers its code into the FPGA during start-up. A user can program its own FPGA code into the flash memory device via the onboard JTAG port.
■For maximum design flexibility, the EVK has 4 free programmable user switches as well as 36 free-of-use FPGA I/Os routed to two connectors.
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PMIC 、 configurable power management IC 、 Evaluation board 、 eight layered PCB |
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Evaluation Board User's Manual |
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Please see the document for details |
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UQFN48FV6060 |
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English Chinese Chinese and English Japanese |
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July 2022 |
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Rev.001 |
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65UG018E |
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22.5 MB |
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