M12L16161A (2R) Operation Temperature Condition -40°C~85°C 512K x 16Bit x 2Banks Synchronous DRAM
●GENERAL DESCRIPTION
■The M12L16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
●FEATURES
■JEDEC standard 3.3V power supply
■LVTTL compatible with multiplexed address
■Dual banks operation
■MRS cycle with address key programs
▲CAS Latency (2 & 3 )
▲Burst Length (1, 2, 4, 8 & full page)
▲Burst Type (Sequential & Interleave)
■All inputs are sampled at the positive going edge of the system clock
■Burst Read Single-bit Write operation
■DQM for masking
■Auto & self refresh
■32ms refresh period (2K cycle)
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Datasheet |
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Please see the document for details |
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TSOP(II) |
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English Chinese Chinese and English Japanese |
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Oct.2020 |
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Revision :1.1 |
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1 MB |
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