Debugging PolarFire FPGA
● Debugging using Identify
▲ The Identify debug tool integrated into Libero SoC, enables FPGA debugging using an embedded logic analyzer. For more information, see TU0780: Using Identify ME with Libero SoC Tutorial.
● Debugging Processor-based designs using SoftConsole
▲ Soft Console enables debugging of processor-based designs (Mi-V or Cortex-M1 based designs). For more information, see TU0775: PolarFire FPGA: Building a Mi-V Processor Subsystem Tutorialand TU0778: PolarFire FPGA Building a Cortex-M1 Processor Subsystem Tutorial.
● Debugging using SmartDebug
▲ SmartDebug enables the debugging of designs by providing verification and troubleshooting features at the hardware level. It provides access to probe points, Non- Volatile Memory (NVM), fabric and fabric RAM blocks, transceivers, and the DDR controller. These features enable designers to check the state of inputs and outputs in real-time, without any design modification.
▲ The built-in probe points of the PolarFire device and the probe capabilities of SmartDebug enable real-time debug features.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2021/1/19 |
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Revision 7.0 |
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AC479 |
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5.7 MB |
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