SLG47910 Countdown Timer Example
■This application shows how to build a down-counter which can be used as a countdown timer to count down from the user specified value down to 0.
■This application note comes complete with a design file which can be found in the References Section.
●Introduction
■This application shows how a countdown timer works. It explains how to design a down counter (Figure 1) which will count down from a user defined value down to zero. But in such cases where the start value is user defined and the width of the counter cannot be determined, a mathematical function is used to determine the number of bits needed for the width of the counter.
■The following signal names are the PINs that are used in the design.
▲NUMBER -parameter to define the start of the counter
▲clk -input clock signal
▲nreset -input negative reset signal
▲counter-output signal of width [ $clog2() :0 ]
■Using the ForgeFPG Workshop software, the Verilog code was synthesized, and the bit stream was loaded on to the SLG47910 device. The functional waveforms below (see Figure 2) shows the countdown timer counting from 4095(default setup) down to 0
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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May 31, 2022 |
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Rev.1.0 |
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AN-FG-008 |
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531 KB |
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