ADRV9026/ADRV9029 System Development User Guide
This user guide is the main source of information for system engineers and software developers using the Analog Devices, Inc., ADRV902x family of software defined radio transceivers. This family consists of the ADRV9026 integrated quad RF transceiver and the ADRV9029 integrated quad RF transceiver with digital predistortion (DPD) and crest factor reduction (CFR) capability. The content of the user guidecovers all functions that are common to both devices and some that are unique to the ADRV9029 device. Throughout the user guide, the term transceiver is used with functions that are common to both devices. Functions that are unique to the ADRV9029 device use ADRV9029 in the description. This user guide must be used in conjunction with the product data sheets to incorporate all necessary specifications and descriptions when designing these devices into new equipment.
●SYSTEM OVERVIEW
■The ADRV9026 and ADRV9029 are part of a family of highly integrated RF agile transceivers designed for use in small cell, massive MIMO, and macro base station equipment used in advanced communications systems. The transceiver contains four independently controlled transmitters, dedicated observation receiver inputs for monitoring transmitter channel outputs, four independently controlled receivers, integrated synthesizers, and digital signal processing functions to provide a complete transceiver solution. The transceiver provides the high radio performance and low power consumption demanded by cellular infrastructure applications, such as macro 2G/3G/4G/5G and massive MIMO base stations. This user guide is designed to encompass description of all functions available in the these transceivers. Note that some variants may be developed for specific design targets that do not encompass all available functions, therefore, refer to the data sheets for the specific transceiver to determine which features are included. To a void confusion, the term transceiver is used throughout this user guide to refer to any variant that employs a specific function. When a function that applies to a specific device is described, the device part number is used to delineate which transceiver is being described.
■These transceivers are designed to operate over the wide frequency ranges of 650 MHz to 6 GHz. The receiver channels support bandwidth up to 200 MHz with data transfer across (up to) four JESD204B/JESD204C lanes at rates up to 24.33 Gbps (see data sheets for specifications). The transmitter channels operate over the same frequency range as the receivers. Each transmitter channel supports up to 450 MHz synthesis bandwidth with data input across (up to) four JESD204B/JESD204C lanes. In addition, local oscillator (LO) routing allows the transmitters to operate at different frequencies than the receivers for additional flexibility. Two observation receiver channels are included to provide the capability to monitor feedback from the transmitter outputs. The feedback loops can be used to implement error correction, calibration, and signal enhancing algorithms. These receivers operate in the same frequency range as the transmitter channels, and they support up to 450 MHz channel bandwidth to match the output synthesis bandwidth of the transmitter channels. These channels provide digital data paths to the internal ARM processor for use in calibration and signal enhancement algorithms. Multiple fully integrated PLLs are included in the transceiver to provide a high level of flexibility and performance. Two are high performance, low power fractional-N RF synthesizers that can be configured to supply the transmitters and receivers in different configurations. A third fractional-N PLL supports an independent frequency for the observation receiver channels. Other clock PLLs are included to generate the converter and digital clocks for signal processing and communication interfaces.
■The power supply for each block is distributed across four different voltage supplies, three analog voltage supplies and one digital voltage supply. The analog supplies are 1.8 V, 1.3 V, and 1.0 V. These supplies are fed directly to the power inputs for some blocks and buffered byinternal low dropout (LDO) regulators for other functions for maximum performance. The digital processing blocks are supplied by a 1.0 V source. In addition, a 1.8 V supply supplies all GPIO and interface ports that connect with the baseband processor.
■See the functional block diagram in the respective data sheets for a high level view of the functions in each transceiver. Descriptions of each block with setup and control details are provided in subsequent sections of this document.
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integrated quad RF transceiver 、 highly integrated RF agile transceivers |
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2022/6/16 |
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Rev. 0 |
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19.1 MB |
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