MPC5674F: Flash Memory Accessibility Issues for Non-POR Reset
▲Whenever a non-POR reset occurs, it can generate a glitch onthe internal Flash A and B modules clock. There is a chancethat this glitch may result in either (or both) flash modulesbecoming unresponsive.
▲The generation of the clock glitch is conditioned by a 5-degreetemperature window (at high temperature) and voltagewindow which varies from device to device with normalprocess variation.
▲There are three different failure scenarios:
◆ Flash A is impacted or both flashes are impacted
●When Flash A is impacted, the device is not able to exitBoot Assist Monitor (BAM) code and the device willstay in serial boot mode, due to not finding the validreset configuration word (RCHW) in flash memory.There is an active Software Watchdog Timer (SWT)during execution of BAM serial boot code which willassert reset after a duration that is based on the crystalfrequency (see Figure 2).
◆Flash B is impacted and the code is executed from Flash A
●When the code is executed from Flash A and Flash B is impacted and is accessed an exception (machine check—IVOR1) is generated.
◆ Flash B is impacted and the code is also executed from Flash B
●When the code is executed from Flash B (the RCHW in Flash A is pointing the code execution into Flash B) and FlashB is stuck, the device stays in BAM code because the exception handler triggered by flash issue is part of BAM code.Software Watchdog Timer (SWT) is configurable during execution of BAM exception handler that is based on thecrystal frequency (see Figure 3).
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Technical Documentation |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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11/2019 |
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Rev. 1 |
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EB00901 |
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493 KB |
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