A Physical Nano-crystal Erase Model
■Non-volatile memories based on charge trapping in a layer of silicon nitride (a SONOS device) or nano-crystalline silicon offer a means to scale the tunnel oxide layer thinner than that in conventional floating-gate device since both of these devices are resistant to charge loss due to isolated defects. Nonetheless, reliability still improves as the tunnel oxide is thickened. As shown previously, tunnel erase in SONOS is limited by the saturation of the threshold voltage with gate bias and tunnel oxide thickness that cannot be mitigated by varying the stack composition. The nano-crystal device, however, does not show this limitation on the tunnel erase, and it continues to have acceptable erase performance with a tunnel oxide sufficiently thick for reliable operation. Here we present a model to illustrate how the nano-crystal device achieves this result.
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Technical Documentation |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2004/10/16 |
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240 KB |
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