MIPI CSI-2 Transmitter Subsystem Product Guide
■The Mobile Industry Processor Interface (MIPI) Camera Serial Interface (CSI-2) TX subsystem implements a CSI-2 transmitter interface [Ref 1]with underlying MIPI DPHY standard v1.2. The CSI-2 TX subsystem packs the incoming pixel data to CSI-2 packets with the required pixel to byte conversion, header and footer insertion. Also generates the required frame and line marker packets. These packets are then sent over DPHY interface for transmission.
●Features
■Support for 1 to 4 D-PHY lanes
■Maximum data rate of 3.2 Gb/s for Versal™ ACAPs and 2.5 Gb/s for UltraScale+™ devices
■Multiple data type support (RAW, RGB, YUV, User defined)
■Support for single, dual, quad pixel modes
■Support for 1 to 4 virtual channels
■Low power state (LP) insertion between the packets
■Ultra low power state (ULPS) mode generation using register access
■Interrupt generation to indicate subsystem status information
■AXI4-Lite interface for register access to configure different subsystem options
■Configurable Line Start/Line End packet generation
■Configurable selection of D-PHY register interface
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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June 30, 2021 |
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v2.2 |
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PG260 |
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1.6 MB |
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