Key Steps to Design A Compact, High-Efficiency PFC Stage Using NCP1623A
■This paper describes the key steps to rapidly design a CrM/DCM PFC stage driven by the NCP1623. The process is illustrated in a practical 100−W, universal mains application:
■Maximum Output Power: 100 W
■Rms Line Voltage Range: from 90 V to 264 V
■Regulation output voltage:
▲250 V in low line (115−V mains)
▲390 V in high line (230−V mains)
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Application note & Design Guide |
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Please see the document for details |
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SOIC−8;TSOP−6;TSOP6;SOIC8 |
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English Chinese Chinese and English Japanese |
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2022/3/8 |
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Rev. 0 |
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AND90156/D |
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119 KB |
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