74AUP2G0604 Low-power inverting buffer with open-drain and inverter Product data sheet
■The 74AUP2G0604 is a single inverting buffer with open-drain output and a single inverter. It features two input pins (nA), an output pin (2Y) and an open-drain output pin (1Y).
■Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times across the entire V-CC range from 0.8 V to 3.6 V.
■This device ensures a very low static and dynamic power consumption across the entire V-CC range from 0.8 V to 3.6 V.
■This device is fully specified for partial power-down applications using I-OFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
●Features and benefits:
■Wide supply voltage range from 0.8 V to 3.6 V
■High noise immunity
■Complies with JEDEC standards:
▲JESD8-12 (0.8 V to 1.3 V)
▲JESD8-11 (0.9 V to 1.65 V)
▲JESD8-7 (1.2 V to 1.95 V)
▲JESD8-5 (1.8 V to 2.7 V)
▲JESD8-B (2.7 V to 3.6 V)
■ESD protection:
▲HBM JESD22-A114F Class 3A exceeds 5000 V
▲MM JESD22-A115-A exceeds 200 V
▲CDM JESD22-C101E exceeds 1000 V
■Low static power consumption; I-CC = 0.9 μA (maximum)
■Latch-up performance exceeds 100 mA per JESD 78 Class II
■Inputs accept voltages up to 3.6 V
■Low noise overshoot and undershoot < 10 % of V-CC
■I-OFF circuitry provides partial power-down mode operation
■Multiple package options
■Specified from -40 °C to +85 °C and -40 °C to +125 °C
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74AUP2G0604 、 74AUP2G0604GW 、 74AUP2G0604GM 、 74AUP2G0604GN 、 74AUP2G0604GS |
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Datasheet |
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Please see the document for details |
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TSSOP6;XSON6;SOT363-2;SOT886;SOT1115;SOT1202 |
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English Chinese Chinese and English Japanese |
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31 January 2022 |
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Rev. 3 |
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251 KB |
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