EV10AS180A Low Power L‐Band 10‐bit 1.5GSps ADC ANALOG to DIGITAL CONVERTER

2022-03-28
●The EV10AS180A is a 10‐bit 1.5 GSps ADC. The device includes a front‐end Track and Hold stage (T/H), followed by an analog encoding stage (Analog Quantizer) which outputs analog residues resulting from analog quantization. Successive banks of latches regenerate the analog residues into logical levels before entering an error correction circuitry and a resynchronization stage followed by a DEMUX with 100Ω differential output buffers.
●MAIN FEATURES:
■Single Core ADC Architecture with 10‐bit Resolution Integrating a Selectable 1:1/2/4 DEMUX
■1.5 GSps Guaranteed Conversion Rate
■Differential Input Clock (AC Coupled)
■Analog Input Voltage: 500 mVpp Differential Full Scale (AC Coupled)
■Analog and Clock Input Impedance: 100 Differential
■LVDS Differential Output Data with Swing Adjustment and Data Ready
■Fine Adjustment of ADC Gain, Offset
■Fine Adjustment of Sampling Delay for Interleaving
■Static and Dynamic Test Mode for ADC and DEMUX
■Data Ready Common to the 4 Output Ports
■1.75W Power Dissipation (1:2 Ratio with Standard LVDS Output Swing)
■Power Supply: 5.2V, 3.3V and 2.5V (Output Buffers)
■LGA255, Ci‐CGA255 or CCGA255 Package

TELEDYNE E2V

EV10AS180AEV10AS180AMGSD/TEV10AS180AMGS9NB1EV10AS180AGS‐EBEV10AS180AMLGD/TEV10AS180AMLG9NB1EV10AS180AMGCD/TEV10AS180AMGC9NB1EV10AS180AMLGEV10AS180AMGCEV10AS80AMGS-VEVX10AS180AGSEVX10AS180ALGEVX10AS180AGCEV10AS180AMLG‐VEV10AS80AMGS‐VEV10AS180AMGC‐V

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Low Power L‐Band 10‐bit 1.5GSps ADCADC

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Datasheet

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Please see the document for details

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LGA255;Ci‐CGA255;CCGA255

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11/15

Revision E

DS1096;1096E–BDC

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