54LS109/DM54LS109A/DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs
■This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is high or low as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
●Features
■Alternate Military/ Aerospace device (54LS109) is available. Contact a National Semiconductor Sales Office/Distributor for specifications.
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54LS109 、 DM54LS109A 、 DM74LS109A 、 54LS109DMQB 、 54LS109FMQB 、 DM54LS109AJ 、 DM54LS109AW 、 DM74LS109AM 、 DM74LS109AN 、 DM54LS 、 54LS 、 DM74LS |
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Datasheet |
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Please see the document for details |
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DIP |
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English Chinese Chinese and English Japanese |
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June 1989 |
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TL/F/6368 |
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135 KB |
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