GDQ2BFAA DDR4 SDRAM
●Power supply : VDD = VDDQ = 1.2V (1.14V to 1.26V); VPP = 2.5V (2.375V to 2.75V)
●JEDEC standard package: x16 96-ball FBGA
●Array Configuration : 8 banks (x16) 2 groups of 4 banks
●8n-bit prefetch architecture
●Burst Length (BL): 8 and 4 with Burst Chop (BC)
●Programmable CAS Latency (CL)
●Programmable CAS Write Latency (CWL)
●Internal generated Vref for data inputs
●On-Die Termination (ODT) : Support Nominal, Park and Dynamic ODT
●Differential clock and data strobe inputs (CK_t ,CK_c; DQS_t, DQS_c)
●Interface: 1.2V Pseudo Open Drain (POD) IO
●Per DRAM Addressability (PDA)
●Data Bus Inversion (DBI)
●Data Mask (DM) for write data
●Maximum Power Saving Mode (MPSM)
●Programmable Partial Array Self-Refresh (PASR)
●Asynchronous reset for power up
●Precharge: Auto precharge option for each burst access
●Operating case temperature :-40°C≤TCase ≤95°C
●Support auto-refresh and self-refresh mode
●Average Refresh Period:
◆7.8μs at -40°C≤TCase ≤85°C
◆3.9μs at 85°C< TCase ≤95°C
●Fine granularity refresh 2x, 4x mode for smaller tRFC
●Programmable data strobe preambles
●Command Address (CA) Parity is supported
●Write Cyclic Redundancy Code (CRC)is supported
●hPPR and sPPR are supported
●Connectivity test mode (TEN) is supported
●Gear Down Mode
●Output driver calibration through ZQ pin (RZQ: 240ohm ± 1%)
●JEDEC JESD-79-4 compliant
●RoHS compliant
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GDQ2BFAA 、 GDQ2BFAA-CQ 、 GDQ2BFAA-CE 、 GDQ2BFAA-CJ 、 GDQ2BFAA-WQ 、 GDQ2BFAA-WJ |
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Datasheet |
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Please see the document for details |
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96-ball FBGA |
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English Chinese Chinese and English Japanese |
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2021-11-2 |
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Rev1.3 |
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DS-00808-GDQ2BFAA |
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8.2 MB |
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