On-Chip Oversampling for the Analog Devices, Inc., AD7380 Family of SAR ADCs

PublishTime：2021-12-15

This application note discusses on-chip oversampling in successive approximation register (SAR), analog-to-digital converters (ADCs). Two common oversampling techniques are normal average and rolling average. These techniques are performed within the AD7380/AD7381 and its family of high throughput rate SAR ADCs so that averaged conversion data is directly available, and so that there is less of a burden on the digital controller, which is an advantage in data acquisition systems.
In a precision data acquisition system, the higher the signal-to-noise ratio (SNR) and the effective number of bits (ENOB), the better the system is at measuring the signal power in the presence of broadband noise.
Noise can degrade system performance. Some ways to reduce noise are to replace the system with a higher resolution ADC, such as an Σ-Δ ADC or SAR ADC, or to oversample and use digital filtering techniques.
The oversampling technique has a history within Σ-Δ ADCs architecture design. An Σ-Δ ADC is constructed from aΣ modulator and a subsequent digital signal processing block, or digital filter. The Σ modulator can be as small as a single bit quantizer to collect thousands of samples and then decimate those samples to achieve a high resolution conversion result.The more samples averaged, the more resolution achievable, resulting in the conversion being closer to the sampled value. Some common Σ-Δ applications are temperature monitoring and weigh scale measurement systems.
Σ-Δ ADC architectures rely on sampling smaller charge at much higher rates than the bandwidth of interest. Taking more samples but with smaller bites. The oversampling range of a typical Σ-Δ ADC falls between 32× up to 1000× the signal of interest. The outcome of oversampling combined with noise shaping (modulation scheme) moves in-band noise out of the bandwidths of interest. The noise moved to higher bandwidths then gets filtered out digitally. The outcome is lower noise and higher resolution in the bandwidth of interest. Each conversion result from the Σ-Δ ADC comes about because of smaller but more frequent sampling events.
SAR ADCs use successive approximation to determine the result. SAR ADCs use a step by step approach to establish what each bit of the digital representation is of a single sampling instant. The SAR employs a charge redistribution capacitor and a digital-to-analog converter (DAC) array. The sampled data is compared to each of the binary weighted capacitive arrays. The total number of binary weighted capacitors determines the number of bits or resolution of the SAR ADC. The conversion processis controlled by a high speed internal clock and the capacitive DAC array, which is able to rapidly convert changing signals. SAR ADCs are used in data acquisition systems that require wide bandwidths.
A SAR ADC typically converts a single instance in time providing a digital answer that relates to a specific time instant. With the advent of faster SAR converters, there is an increased usage of oversampling to improve resolutions for the key bandwidths of interest. Often today where SAR ADCs use the oversampling technique, the technique is performed via post processing on microcontrollers or the field programmable gate arrays (FPGAs). Analog Devices, Inc., offers an oversampling feature built in to its series of SAR ADCs. This oversampling feature improves noise performance, simplifies interface requirements, and allows users to employ out of the box without the need for the design and resource intensive averaging of FPGAs or microcontrollers. The oversampling features also maximizes data processing performance at a manageable data rate

Brand of Product：	ADI
Part#：	AD7380 Family 、 AD7380 、 AD7381 、 AD7386 、 AD7387 、 AD7388 More Part#
Product Category：	analog-to-digital converters 、 SAR ADCs More
Application：	More
Data Type：	Application note & Design Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	6/2020
Version Number：	Rev. 0
Data Encoding：	AN-2003
Data Size：	195 KB

Data section preview(2pages)

- The full preview is over. If you want to read the whole 10 page document,please Sign in/Register -

Download

+1 Like
Add to Favorites

Recommend

New Products & Solutions

More>

Technical Resources

More>

All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.

Integrated Circuits