LPC55S2x/LPC552x ARM Cortex-M33 based microcontroller data sheet
■The LPC55S2x/LPC552x is an ARM Cortex-M33 based microcontroller for embedded applications. These devices include a CASPER Crypto/FFT engine, up to 256 KB of on-chip SRAM, up to 512 KB on-chip flash, PRINCE module for on-the-fly flash encryption/decryption, high-speed and full-speed USB host and device interface with crystal-less operation for full-speed, SD/MMC/SDIO interface, five general-purpose timers, one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), nine flexible serial communication peripherals (which can be configured as a USART, SPI, high speed SPI, I2C, or I2S interface), Programmable Logic Unit (PLU), one 16-bit 1.0 Msamples/sec ADC capable of simultaneous conversions, comparator, and temperature sensor.
■To support security requirements, the LPC55S2x/LPC552x also offers support for secure boot, HASH, AES, RSA, UUID, dynamic encrypt and decrypt, debug authentication, and TBSA compliance.
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LPC55S2x 、 LPC552x 、 LPC55S28JBD100 、 LPC55S26JBD100 、 LPC55S28JEV98 、 LPC55S26JEV98 、 LPC55S28JBD64 、 LPC55S26JBD64 、 LPC5528JBD100 、 LPC5526JBD100 、 LPC5528JEV98 、 LPC5526JEV98 、 LPC5528JBD64 、 LPC5526JBD64 |
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Datasheet |
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Please see the document for details |
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HLQFP100;VFBGA98;HTQFP64;SOT1570-3;SOT1982-1;SOT855-5 |
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English Chinese Chinese and English Japanese |
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9 December 2020 |
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Rev. 2.0 |
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4.8 MB |
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