FPGA-IPUG-02062-1.4 ADC Sequencer Module - Lattice Radiant Software User Guide
■Analog to Digital Converter (ADC) with Successive Approximation Resistor/Capacitor (SAR) architecture is one of the most common and widely used types of ADCs. It is commonly used in data-acquisition, industrial-control and instrumentation applications, where ultra-high speed is not necessary. ADCs with SAR architecture have good resolution and moderately high sampling rate.
The Lattice Semiconductor ADC Sequencer Module incorporates two 12-bit resolution and 1 MSPS conversion speed ADCs. Each IP is implemented with SAR architecture and supports both Continuous and Single-Pass conversion modes. The SAR ADC operates by using a binary search algorithm to converge on the input signal. The Lattice ADC IP includes a configurable Sequencer Module, which automates ADC data acquisition process. ADC IP also supports configurable over/under voltage and temperature alarming function. Both the Sequencer Module and alarm functions can be configured through the Lattice Memory Mapped Interface (when LMMI is enabled) and through the user interface.
The ADC IP can be targeted to the Lattice FPGA devices built on the Lattice Nexus™ platform and is implemented using the Lattice Radiant™ software Place and Route tool integrated with the either Synplify Pro® or Lattice LSE synthesis tool.
●Features:
■The key features of the ADC Sequencer Module include:
▲12-bit or better resolution
▲1 MSPS sampling rate
▲Selectable input signal source among 24 input channels, 12 for each ADCO and ADC1 cores
▲Uni-polar or bi-polar input conversion option
▲SNDR - 68 dB with 50 kHz input signal at 1 MSPS conversion speed
▲THD - 76 dB with 50 kHz input signal at 1 MSPS conversion speed
▲INL < +/- 2LSB, DNL < +/- 1 LSB
▲Option for internal 1.1 V to 1.3 V or external 1.0 V to 1.8 V reference voltage
▲Input signal range 0 V to 1.8 V (1.2 V with internal reference case, 1.8 V with external ref)
▲Vdd = 1.8V for Analog, Vdd=1.0V/0.9V for Digital
▲Power < 1 mW at maximum conversion speed
▲Power Down Mode for sleep
▲Sequential or simultaneous sampling option between two ADCs
▲Internal junction temperature monitoring diode
▲Five power supplies' voltage monitoring
▲Three continuous-time comparators
▲Configurable automated data acquisition process
▲Configurable Over/Under Voltage alarm function
▲AXI-4 based Interface along with the native output signals supports ADC IP output data flow
▲LMMI based Interface for ADC IP output data flow support
▲Up to 16 ADC GPIO differential pairs (11 - for LIFCL-17)
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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June 2021 |
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FPGA-IPUG-02062-1.4 |
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2.2 MB |
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