APPENDIX D REGISTER SUMMARY
Except for central processing unit resources, information is presented in the intermodule bus address order shown in Table D-1.
Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte block. The state of the module mapping (MM) bit in the SIM configuration register (SIMCR) determines where the control register block is located in the system memory map. When MM = 0, register addresses range from $7FF000 to $7FFFFF; when MM = 1, register addresses range from $FFF000 to $FFFFFF.
In the module memory maps in this appendix, the “Access” column specifies which registers are accessible when the CPU32 is in supervisor mode only and which registers can be assigned to either supervisor or user mode.
|
|
User's Guide |
|
|
|
Please see the document for details |
|
|
|
|
|
|
|
English Chinese Chinese and English Japanese |
|
15 Oct 2000 |
|
Rev. 15 Oct 2000 |
|
|
|
2 MB |
- +1 Like
- Add to Favorites
Recommend
All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.