nRF52832 Revision 3 Errata
●The document indicates which anomalies are fixed, inherited, or new compared to revision Revision 2.
●Added: No. 12. “Reference ladder is not correctly calibrated”
●Added: No. 15. “RAM[x].POWERSET/CLR read as zero”
●Added: No. 20. “Register values are invalid”
●Added: No. 31. “Calibration values are not correctly loaded from FICR at reset”
●Added: No. 36. “Some registers are not reset when expected”
●Added: No. 51. “Aligned stereo slave mode does not work”
●Added: No. 54. “Wrong LRCK polarity in Aligned mode”
●Added: No. 55. “RXPTRUPD and TXPTRUPD events asserted after STOP”
●Added: No. 58. “An additional byte is clocked out when RXD.MAXCNT= 1”
●Added: No. 64. “Only full bytes can be received or transmitted, but supports 4-bit frame transmit”
●Added: No. 66. “Linearity specification not met with default settings”
●Added: No. 67. “Some events cannot be used with the PPI”
●Added: No. 68. “EVENTS_HFCLKSTARTED can be generated before HFCLK is stable”
●Added: No. 72. “TASKS_ACTIVATE cannot be used with the PPI”
●Added: No. 74. “Started events fires prematurely”
●Added: No. 75. “Increased current consumption”
●Added: No. 76. “READY event is set sooner than it should”
●Added: No. 77. “RC oscillator is not calibrated when first started”
●Added: No. 78. “High current consumption when using timer STOP task only”
●Added: No. 79. “ A false EVENTS_FIELDDETECTED event occurs after the field is lost”
●Added: No. 81. “PIN_CNF is not retained when in debug interface mode”
●Added: No. 83. “STOPPED event occurs twice if the STOP task is triggered during a transaction”
●Added: No. 84. “ISOURCE not functional”
●Added: No. 86. “Triggering START task after offset calibration may write a sample to RAM”
●Added: No. 87. “Unexpected wake from System ON Idle when using FPU”
●Added: No. 88. “Increased current consumption when configured to pause in System ON idle”
●Added: No. 89. “Static 400 μA current while using GPIOTE”
●Added: No. 97. “High current consumption in System ON Idle mode”
●Added: No. 101. “Sleep current increases after soft reset”
●Added: No. 108. “RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode”
●Added: No. 109. “DMA access transfers might be corrupted”
●Added: No. 113. “Single-ended mode with external reference is not functional”
●Added: No. 132. “The LFRC oscillator might not start”
●Added: No. 136. “Bits in RESETREAS are set when they should not be”
●Added: No. 138. “Spurious emission on GPIO exceeds limits in radiated tests”
●Added: No. 141. “HFCLK not stopped when entering SENSE mode”
●Added: No. 143. “False CRC failures on specific addresses”
●Added: No. 146. “LFRC frequency deviation”
●Added: No. 149. “First clock pulse after clock stretching may be too long or too short”
●Added: No. 150. “EVENT_STARTED does not fire”
●Added: No. 155. “IN event may occur more than once on input edge”
●Added: No. 156. “Some CLR tasks give unintentional behavior”
●Added: No. 173. “Writes to LATCH register take several CPU cycles to take effect”
●Added: No. 176. “Flash erase through CTRL-AP fails due to watchdog time-out”
●Added: No. 178. “END event firing too early”
●Added: No. 179. “COMPARE event is generated twice from a single RTC compare match”
●Added: No. 182. “Fixes for anomalies #102, #106, and #107 do not take effect”
●Added: No. 183. “False SEQEND[0] and SEQEND[1] events”
●Added: No. 192. “LFRC frequency offset after calibration”
●Added: No. 194. “STOP task does not switch off all resources”
●Added: No. 196. “PSEL acquires GPIOs regardless of ENABLE”
●Added: No. 201. “EVENTS_HFCLKSTARTED might be generated twice”
●Added: No. 204. “Switching between TX and RX causes unwanted emissions”
●Added: No. 210. “Bits in GPIO LATCH register are incorrectly set to 1”
●Added: No. 212. “Events are not generated when switching from scan mode to no-scan mode with burst enabled”
●Added: No. 213. “WDT configuration is cleared when entering system OFF”
●Added: No. 218. “Frame delay timing is too short after SLP_REQ”
●Added: No. 219. “I2C timing spec is violated at 400 kHz”
●Added: No. 220. “RAM is not ready when written”
●Added: No. 245. “CRC is wrong when data whitening is enabled and address field is included in CRC calculation”
●Added: No. 249. “Access port protection needs software interface configuration”
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Errata |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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09.09.2021 |
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Revision 3 v1.0 |
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4397_883 |
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570 KB |
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