Libero® SoC v2021.2 Macro Library User Guide for SmartFusion®2 FPGA and IGLOO®2 FPGA
●This macro library guide supports the SmartFusion®2 FPGA and IGLOO®2 FPGA families. See the Microchip website for macro guides for other families.
●This guide follows a naming convention for sequential macros that is unambiguous and extensible, making it possible to understand the function of the macros by their name alone.
●The first two mandatory characters of the macro name indicates the basic macro function:
◆DF - D-type flip-flop
◆DL - D-type latch
●The next mandatory character indicates the output polarity:
◆I - output inverted (QN with bubble)
◆N - output non-inverted (Q without bubble)
●The next mandatory number indicates the polarity of the clock or gate:
◆1 - rising edge triggered flip-flop or transparent high latch (non-bubbled)
◆0 - falling edge triggered flip-flop or transparent low latch (bubbled)
●The next two optional characters indicate the polarity of the Enable pin, if present:
◆E0 - active low enable (bubbled)
◆E1 - active high enable (non-bubbled)
●The next two optional characters indicate the polarity of the asynchronous Preset pin, if present:
◆P0 - active low asynchronous preset (bubbled)
◆P1 - active high asynchronous preset (non-bubbled)
●The next two optional characters indicate the polarity of the asynchronous Clear pin, if present:
◆C0 - active low asynchronous clear (bubbled)
◆C1 - active high asynchronous clear (non-bubbled)
●AAll sequential and combinatorial macros (except MX4 and XOR8) use one logic element in the PolarFire® FPGA family..
●For example, the macro DFN1E1C0 indicates a D-type flip-flop (DF) with a non-inverted (N) Q output, positive-edge triggered (1), with Active High Clock Enable (E1) and Active Low Asychronous Clear (C0). See the following tabble.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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08/2021 |
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Revision C |
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DS50003079C |
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1.1 MB |
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