nRF5340 Engineering D Errata

PublishTime：2021-11-30

●This Errata document contains anomalies for the nRF5340 chip, revision Engineering D (CLAA-DA0, QKAA-DB0).
●The document indicates which anomalies are fixed, inherited, or new compared to revision Engineering A.
●Added: No. 6. “Disabling instruction cache causes skip of next instruction”
●Added: No. 43. “Reading QSPI registers after XIP might halt application CPU”
●Added: No. 44. “TASKS_RESUME impacts UARTE”
●Added: No. 47. “I2C timing spec is violated at 400 kHz”
●Added: No. 55. “Bits in RESETREAS are set when they should not be”
●Added: No. 65. “Events are not generated when switching from scan mode to no-scan mode with BURST disabled”
●Added: No. 70. “Event FIELDDETECTED may be generated too early”
●Added: No. 71. “Frame delay timing is too short after SLP_REQ”
●Added: No. 75. “False SEQEND[0] and SEQEND[1] events are generated”
●Added: No. 76. “Non-secure code can detect secure events”
●Added: No. 87. “RSSI parameter adjustment”
●Added: No. 99. “Mode 3 is not functional at 96 MHz”
●Added: No. 112. “24-bit sample in a 32-bit half-frame is received incorrectly”
●Added: No. 113. “Reading DTX in MODECNF0 gives incorrect value”
●Added: No. 117. “Changing MODE requires additional configuration”
●Added: No. 119. “Writes to LATCH register take several CPU cycles to take effect”
●Added: No. 121. “Configuration of peripheral requires additional steps”
●Added: No. 122. “Successive triggering of CTRLAP.ERASEALL has no effect”

Brand of Product：	Nordic Semiconductor
Part#：	nRF5340 More Part#
Product Category：	More
Application：	More
Data Type：	Errata More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	03.12.2020
Version Number：	Engineering D v1.0
Data Encoding：	4406_652
Data Size：	299 KB

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