AN2478 Using the SDRAM Controller MC9328MX1, MC9328MXL, and MC9328MXS Application Note
■This document provides a comprehensive discussion on how the Freescale Semiconductor’s i.MX applications processors interface to different configurations of SDRAM memory devices and how to initialize these devices and their mode registers. By providing an overview of the i.MX SDRAM Controller and its address multiplexing scheme, systems designers will better understand how to interface their SDRAM memory with the i.MX processors. ■This document provides several examples of different SDRAM memory configurations and provides an overview of the SDRAM memory initialization scheme and mode register programming aimed to further increase system designer understanding on how to use the i.MX SDRAM Controller. The i.MX devices affected by this discussion are:
▲MC9328MX1
▲MC9328MXL
▲MC9328MXS
■The examples provided in this document assume that the number of rows and columns for each given SDRAM density follow the JEDEC standard. The SDRAM Controller can interface to SDRAMS that do not follow the JEDEC standards for row and column sizes, however the user must ensure that the SDRAM Control Register bits ROW and COL are programmed to the appropriate number of rows and columns given in the SDRAM data sheet. These examples do not cover non-JEDEC standard SDRAMS
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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02/2007 |
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Rev. 5 |
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AN2478 |
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2.7 MB |
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