Core8051s v2.4 Release Notes
●Features
■Core8051s is a highly configurable processor that can be used to build compact and efficient microcontroller subsystems. To minimize area, the inbuilt 8051 peripherals are not present within the processor. The external SFR interface normally present on 8051 microcontrollers is replaced by an advanced peripheral bus (APB) v3.0 interface. This allows the user to decide which peripherals to add to the system.
▲Key Features
◆Configurable 8-bit processor
◆Can be targeted by 8051 C compilers, such as Keil or SDCC. SDCC is bundled with Actel's SoftConsole software development environment.
◆Inbuilt 8051 peripherals such as timer, I/O ports, and serial channel are not included. APB peripherals can be optionally included.
◆APB v3.0 interface on the processor for connecting to APB peripherals
◆On-chip instrumentation (OCI) debug logic can be optionally included to facilitate JTAG based debugging.
◆The internal 256x8 RAM within the processor can be implemented using RAM macro blocks or registers (FPGA tiles).
◆Multiple configurable options for optimal implementation
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Development Environment（Software/Firmware） |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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September 2010 |
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51300042-3 |
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162 KB |
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