RTG4™ Two-Port Large SRAM Configuration User Guide
A Two-Port Large SRAM allows write access on one port and read access on the other port (see the following figure). The core configurator cascades Large SRAM blocks automatically to create wide and deep memories by choosing the most efficient aspect ratio. It also handles the grounding of unused bits. The core configurator supports the generation of memories that have different Read and Write aspect ratios.
Two-Port Large SRAM is synchronous with read and write operations, setting up the addresses as well as writing and reading the data. The memory write and read operations are triggered at the rising edge of the clock. The address,data, write-enable, and read-enable inputs are registered.
An optional pipeline register is available at the read data port to improve the clock-to-out delay. When ECC is enabled, output flags are generated to indicate single-bit-correct and double-bit-detect.
For more information about Two-Port Large SRAM, refer to the RTG4 User Guide.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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11/2020 |
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Revision A |
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DS50003071A |
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337 KB |
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