SmartFusion®2, IGLOO®2, and RTG4™ PDC Commands User Guide

PublishTime：2021-11-25

In the FPGA design world, constraint files are as important as design source files. Physical design constraints (PDC) are used to constrain the I/O attributes, placement, and routing during the physical layout phase.
You can enter PDC commands manually using the Libero SoC Text Editor. PDC commands can also be generated using Libero SoC's interactive tools. The I/O Attribute Editor is the interactive tool for making I/O attribute changes,and the Chip Planner is the interactive tool for making floorplanning changes.
When changes are made in the I/O Attribute Editor or the Chip Planner, the PDC file(s) are updated to reflect the changes. These PDC commands can be used as part of a script file to constrain the Place and Route step of your design.

Brand of Product：	MICROSEMI
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Data Type：	User's Guide More
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Language：	English Chinese Chinese and English Japanese
Date of Creation：	11/2020
Version Number：	Revision A
Data Encoding：	DS50003096A
Data Size：	393 KB

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