Libero® SoC v2021.1 PDC Commands Reference Guide for PolarFire® and PolarFire SoC FPGAs

PublishTime：2021-11-25

In the FPGA design world, constraint files are as important as design source files. Physical design constraints (PDC)are used to constrain I/O attributes, placement, and routing during the physical layout phase.
You can enter PDC commands manually using the Libero® SoC Text Editor. PDC commands can also be generated by the Libero SoC interactive tools. The I/O Attribute Editor is the interactive tool for making I/O attributes changes and the Chip Planner is the interactive tool for making floor-planning changes. When changes are made in the I/O Attribute Editor or the Chip Planner, the PDC file(s) are updated to reflect these changes. These PDC commands can be used as part of a script file to constrain the Place and Route step of your design.

Brand of Product：	MICROSEMI
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Product Category：	More
Application：	More
Data Type：	User's Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
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Language：	English Chinese Chinese and English Japanese
Date of Creation：	04/2021
Version Number：	Revision B
Data Encoding：	DS50003074B
Data Size：	337 KB

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