RTG4 DDR Memory Controller Configuration User Guide

PublishTime：2021-11-25

The RTG4 FPGA has two DDR memory controller blocks located on the East and West side of the chip identified as:
●East FDDR
●West FDDR
The DDR controllers control off-chip DDR memories.
To fully configure the RTG4 DDR memory controller you must:
●Use the RTG4 DDR Memory Controller Configurator to configure the DDR Controller, select its datapath bus interface (AXI or AHB), and select the DDR clock frequency as well as the fabric datapath clock frequency.
●Set the register values for the DDR controller registers to match your external DDR memory characteristics.
●Instantiate the DDR controller as part of a user application and make datapath connections.
●Connect the DDR controller's APB configuration interface as defined by the Peripheral Initialization solution.

Brand of Product：	MICROSEMI
Part#：	RTG4 More Part#
Product Category：	DDR Memory Controller More
Application：	More
Data Type：	User's Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	2019
Version Number：	Revision 2.0
Data Encoding：	5-02-00589-2
Data Size：	556 KB

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