SmartTime Static Timing Analyzer Libero SoC v12.1 and later User Guide

2021-11-25
SmartTime is the Libero SoC gate-level static timing analysis tool. With SmartTime, you can perform complete timing analysis of your design to ensure that you meet all timing constraints and that your design operates at the desired speed with the right amount of margin across all operating conditions.
Note: Creation and Editing of timing constraints are now handled in a separate Timing Constraints Editor. See the Timing Constraints Editor User Guide for help with creating and editing timing constraints.

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Static Timing Analyzer

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User's Guide

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