CoreFPU v2.0 Release Notes
■These release notes accompany the production release of CoreFPU v2.0. This document provides details about the features, enhancements, system requirements, supported families, implementations, and known issues and workarounds.
●Features：
■The Core Floating Point Unit (CoreFPU) is designed for floating-point arithmetic and conversion operations for single precision floating point numbers. CoreFPU supports conversion operations like fixed-point to floating-point, floating-point to fixed-point and arithmetic operations like addition, subtraction, and multiplication.
■CoreFPU has following features:
▲Supports single precision floating numbers as per IEEE-754 standard.
▲Conversions
◆Fixed Point to Floating Point Conversion
◆Floating Point to Fixed Point Conversion
▲Arithmetic Operations
◆Floating Point Addition
◆Floating Point Subtraction
◆Floating point Multiplication
▲Provides flags for Overflow, Infinity, and Not-a-Number (NaN) for floating point numbers.
▲Fully pipelined implementation of arithmetic operations.
▲Provision to configure the core for design requirements.
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Development Environment（Software/Firmware） |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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4/20 |
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Revision 1.0 |
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RN0230 |
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185 KB |
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