MSC8112 Device Errata for Mask 2K98M

PublishTime：2021-11-23

The Ethernet controller Rx FIFO can encounter an overflow situation due to a system busy condition caused by heavy accesses to SDRAM memory from competing devices and the Ethernet controller. Such conditions can increase the time required to access the memory, which increases the possibility of an overflow condition due to a heavy line load. Note that a system busy condition is not due to a lack of Rx buffers as indicated by the IEVENT[BSY] bit or a GRS condition indicated by the IEVENT[GRSC] bit. The symptom is that the receiver may drop frames but not indicate a dropped frame condition. In some cases, the receiver may hang. When the receiver enters a hung state, all incoming frames are dropped and the RDRP register logs them as dropped frames. Only an external HRESET can make the Ethernet controller exit this condition.

Brand of Product：	NXP
Part#：	MSC8112 More Part#
Product Category：	More
Application：	More
Data Type：	Errata More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	1/16/2009
Version Number：	Rev. 1
Data Encoding：	MSC8112CE2K98M
Data Size：	37 KB

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