PXS20 Microcontroller Reference Manual
The PXS20 is designed for applications requiring a high Safety Integrity Level (SIL).
All devices in this family are built around a dual core safety platform with an innovative safety concept that reduces system cost and effort for the customer to achieve IEC61508 and other corresponding certifications of their system. In order to minimize software overhead and improve operational reliability, all major systems such as CPU core, DMA controller, interrupt controller, crossbar bus system, memory systems, peripheral systems, and memory protection unit, include built in redundancy and or robust system monitoring. Lock Step Redundancy Checking Units are implemented at each output of this Sphere of Replication (SoR). ECC is available for on-chip RAM and flash memories. A programmable fault collection and control unit monitors the integrity status of the device and provides flexible safe state control.
The host processor core of the PXS20 is the latest CPU from the e200 family of compatible Power Architecture cores. The e200z4d 5-stage pipeline dual issue core provides a very high level of efficiency, allowing high performance with minimum power consumption.
The peripheral set provides high-end electrical motor control capability with very low CPU intervention, thanks to the on-chip Cross Triggering Unit (CTU).
This device incorporates high-performance 90 nm embedded flash-memory technology to provide substantial cost reduction per feature and significant performance improvement.
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User's Guide |
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Please see the document for details |
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LQFP |
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English Chinese Chinese and English Japanese |
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06/2011 |
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Rev. 1 |
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PXS20RM |
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20.6 MB |
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