PXS20 Microcontroller Reference Manual

2021-11-23
The PXS20 series microcontrollers are system-on-chip devices that are built on Power Architecture®technology, are 100% user-mode compatible with the classic Power Architecture instruction set, contain enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital signal processing (DSP), and integrate technologies to support highly reliable and safe operation across a range of industrial, medical and transportation safety critical applications. These microcontrollers include a rich set of peripherals for complex real time control, such as an enhanced timer unit, analog-to-digital converters, and multiple serial communications modules.
The PXS20 is designed for applications requiring a high Safety Integrity Level (SIL).
All devices in this family are built around a dual core safety platform with an innovative safety concept that reduces system cost and effort for the customer to achieve IEC61508 and other corresponding certifications of their system. In order to minimize software overhead and improve operational reliability, all major systems such as CPU core, DMA controller, interrupt controller, crossbar bus system, memory systems, peripheral systems, and memory protection unit, include built in redundancy and or robust system monitoring. Lock Step Redundancy Checking Units are implemented at each output of this Sphere of Replication (SoR). ECC is available for on-chip RAM and flash memories. A programmable fault collection and control unit monitors the integrity status of the device and provides flexible safe state control.
The host processor core of the PXS20 is the latest CPU from the e200 family of compatible Power Architecture cores. The e200z4d 5-stage pipeline dual issue core provides a very high level of efficiency, allowing high performance with minimum power consumption.
The peripheral set provides high-end electrical motor control capability with very low CPU intervention, thanks to the on-chip Cross Triggering Unit (CTU).
This device incorporates high-performance 90 nm embedded flash-memory technology to provide substantial cost reduction per feature and significant performance improvement.

NXP

PXS20PXS2005PXS2010

More

Part#

Microcontroller

More

More

User's Guide

More

More

Please see the document for details

More

More

LQFP

English Chinese Chinese and English Japanese

06/2011

Rev. 1

PXS20RM

20.6 MB

- The full preview is over. If you want to read the whole 1368 page document,please Sign in/Register -
  • +1 Like
  • Add to Favorites

Recommend

All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.

Contact Us

Email: