PXR40 Microcontroller Reference Manual

PublishTime：2021-11-23

The PXR40 device targets real-time, high performance applications. It is built upon the 90 nm CMOS technology node. This document describes the features of the PXR40 and highlights important electrical and physical characteristics of the device.
The e200z7 core of the PXR40 is compatible with the Power Architecture® Book E architecture. It is 100% user-mode compatible (with floating point library) with the classic PowerPC instruction set. The Book E architecture has enhancements that improve the architecture’s fit in embedded applications. In addition to the classic PowerPC instruction set, this core also has additional instruction support for digital signal processing (DSP) and SIMD operations.
The PXR40 has two levels of memory hierarchy, a 32 KB Harvard architecture cache and a 256 KB on-chip SRAM. 4 MB of internal flash memory is provided. The features of the final, production-targeted device version are listed below.

Brand of Product：	NXP
Part#：	PXR40 、 PXR4030 、 PXR4040 More Part#
Product Category：	Microcontroller More
Application：	More
Data Type：	User's Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：	PBGA
Language：	English Chinese Chinese and English Japanese
Date of Creation：	06/2011
Version Number：	Rev. 1
Data Encoding：	PXR40RM
Data Size：	21.3 MB

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