Interfacing the QUICC to a MCI 516400 (4 M x4 10/12 column/row) DRAM

PublishTime：2021-11-22

●One of the most useful functions of the SIM block of the MC68360 is the Memory Controller. This enables the MC68360 to interface gluelessly to EPROM, SRAM and DRAM. The DRAM controller can easily be configured for DRAM arrays with an equally divided number of rows and columns, for example the MCM54400A with 10 rows and 10 columns. However, many 16M DRAMs have 12 rows and 10 columns, to reduce power consumption.The MCM516400 is one such device. This application note illustrates how the QUICC DRAM Controller may be used to interface gluelessly to the MCM516400.
●For 16M DRAMs, there is a trade off between ease of addressing versus power consumption. A 11x11 array is easier to address, but the power consumption is higher, approximately 660mW compared to 495mW in the12x10 array. This represents a 25% saving per device. A typical 32-bit array contains eight MCM516400, so using this topology reduces consumption by 1.3W - a considerable saving. This difference in power consumption is due to the internal topology of the memory array. Each access to the 11x11 array requires more internal blocks to be turned on than are required for the 12x10 array, so consumes more power. In many applications power constraints area major concern, therefore the 12 row by10 column topology is becoming more popular.

Brand of Product：	NXP
Part#：	MC68360 、 MC516400 、 MCM516400 More Part#
Product Category：	QUICC 、 DRAM controller 、 DRAM More
Application：	More
Data Type：	Application note & Design Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	2019/02/07
Version Number：
Data Encoding：	AN2029
Data Size：	194 KB

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