PowerPC Microprocessor Clock Modes
■Low-speed, low-cost memory systems with economical, low-cost processors.
■Low-speed, economical memory systems isolated from very high-speed processor cores and internal cache.
■High-speed, performance oriented memory systems with maximum achievable processor core and internal cache frequencies.
■Embedded systems with unusual bus speeds dictated by system requirements other than the processor.
●This document is divided into two parts:
■General information
▲This section discusses a variety of issues including:
◆ PowerPC microprocessor clocking operation
◆ PowerPC device numbering methodology
◆ Various test issues and methodology
◆Special timing considerations
■Appendixes—This section provides several graphs of PowerPC microprocessor clock relationships.
●In this document, the term “MPC60x” is used to denote a 32-bit microprocessor from the PowerPCarchitecture family, including the PowerPC 602™, PowerPC 603™, PowerPC 603e™, PowerPC 604™,and PowerPC 604e™ microprocessors. MPC60x processors implement the PowerPC architecture as it isspecified for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8,16, and 32 bits, and floating-point data types of 32 and 64 bits (single-precision or double-precision).
MPC60x 、 MPC602 、 MPC603 、 MPC603e 、 MPC604 、 MPC604e 、 MPC105 、 MPC106 、 PID6-603e 、 PID7v-603e |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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