EFM32 Interrupt Handling
■Interrupts are a commonly used technique in microcontrollers allowing CPU-external systems to indicate need for change in CPU execution. Instead of using polling loops to monitor these kinds of events and wasting valuable processing time, interrupts do not require any action from the CPU unless they are triggered.
■When an Interrupt Request (IRQ) is received, the CPU will store its current state before it switches to the Interrupt Service Routine (ISR) (Figure 1.1 (p. 2) ). In older architectures there was only one ISR and SW needed to determine which source triggered the IRQ. In modern architectures like the ARM Cortex-M in the EFM32, each IRQ has its own ISR. The starting address for each ISR is stored in an interrupt vector table.
■When an interrupt is triggered, the CPU automatically jumps to the corresponding address in the vector table which contains an address to the relevant ISR. The service routine then executes the tasks needed to handle the event before the CPU returns to where it left off before the interrupt was received. A common way to acknowledge the interrupt is to clear the interrupt source in the interrupt handler resulting in the IRQ being de-asserted.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2013-09-16 |
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Rev1.04 |
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AN0039 |
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897 KB |
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