PM8658, PM8659 XpressConnect™ PCIe® Gen 5 and CXL™ Retimer Family

PublishTime： 2021-10-14 Manufacturer： Microchip Type： Datasheet Language： English

●Summary:
■XpressConnect™ Retimers provide best-in-class signal conditioning for PCI Express® 5.0 and Compute Express Link™ 1.1/2.0 interconnects and support Intel's® PCIe 5.0 Retimer Supplemental Features and Standard BGA Footprint specification. XpressConnect Retimers triple the reach of PCIe Gen 5 electrical signals with minimal impact to latency to enable the most demanding computational workloads in artificial intelligence, machine learning, communication systems and high-performance computing applications.
■XpressConnect Retimers support x2/x4/x8/x16 bifurcation to connect to a wide range of PCIe and CXL devices. XpressConnect Retimers delivers the industry's lowest latency retimer solution with over 80% lower latency than the PCIe specification to maximize performance for PCIe and CXL devices. XpressConnect Retimers includes comprehensive diagnostics features, multiple configuration options, a simple management interface and low power to reduce total cost of owner-ship during design, bring-up, validation and production.
■XpressConnect Retimers are ideal for enterprise servers, PCIe NVMe enclosures, all Flash NVMe arrays, PCIe fabrics, CXL accelerator/memory solutions, and other applications that require low latency, low power and secure PCIe and CXL retiming.
●Features:
■PCIe and CXL Features
▲Intel PCIe 5.0 Retimer Supplemental Features and Stan-dard BGA Footprint Specification
▲PCIe Express 3.0/4.0/5.0
▲Compute Express Link 1.1/2.0
▲>80% lower latency than PCIe specification
▲Bifurcation/link subdivision (x2/x4/x8/x16)
▲Automatic detection of pseudo port orientation
▲Lane reversal and lane polarity inversion
▲Passive copper and active optical cable support
▲Receiver detection bypass
■Diagnostics and Debug
▲ChipLink™ Diagnostics Tool compatible with Windows®, Linux® and Mac® OS X
▲Real-time eye capture
▲LTSSM logs and triggers
▲PCIe link EQ logs
▲Pattern generation, detection and error injection
▲Receiver lane margining
▲PCIe loopback
▲Real-time error injection
▲PHY-level error counters and TX/RX settings

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