i.MX 8X Using L1 Cache for Cortex-M4 Core

PublishTime：2021-09-07

Introduction:
●The i.MX 8X series takes advantage of the Arm® Cortex®-M4 core with a 16K/16K L1 I/D-Cache. This delivers extremely high performance, regardless of whether the code is executed from the on-chip RAM, external flash, or external memory.
●This document introduces the basic technology of the cache system that includes the L1 cache, memory types, attributes, and MPU (Memory Protection Unit) for the Cortex-M4 core embedded into the i.MX 8X series processors. It guides you on how to use the cache to develop applications running correctly and with high performance. It does not describe the details of the cache system. For more detailed information, see the Arm Cortex-M4 processor user's guide.
●The software used for the example in this documentation is based on the i.MX 8QXP SDK release with the Arm CMSIS implementation. The development environment is the IAR Embedded Workbench 8.40 IDE. The hardware used to verify the example is the MIMX8QXP-MEK board.
Overview:
This chapter describes the i.MX 8X Cortex-M4 system architecture with cache-related parts. It describes the L1 cache behavior, Arm Cortex-M4 defined memory types/attributes, and the MPU (Memory Protection Unit) system. This provides an overview of the i.MX 8X Cortex-M4 core cache system and how it affects the application use cases.

Brand of Product：	NXP
Part#：	i.MX 8X series 、 i.MX 8X More Part#
Product Category：	processors More
Application：	More
Data Type：	Application note & Design Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	1 June 2021
Version Number：	Rev. 0
Data Encoding：	AN13285
Data Size：	280 KB

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