74HC138 3 TO 8 LINE DECODER DEMULTIPLEXER
■The 74HC138 is a high speed CMOS device.
■The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaing seven being high.
■There are two active LOW enable inputs E1 and E2, and one active HIGH enable input E3. The disabled device state results in all outputs being high. The enable state occurs with E1 and E2 asserted low and E3 asserted high.
■The multiple enable lines allow for the parallel expansion of decoders to create 4-to-16 line versions with no additional parts and 5-to-32 versions with the addition of a single inverter.
●Features
■Wide Supply Voltage Range from 2.0V to 6.0V
■Sinks or sources 8mA at V-CC = 4.5V
■CMOS low power consumption
■Schmitt Trigger Action at All Inputs
■Inputs Accept up to 6V
■ESD Protection Tested per JESD 22
▲Exceeds 200-V Machine Model (A115-A)
▲Exceeds 2000-V Human Body Model (A114-A)
▲Exceeds 1000-V Charged Device Model (C101C)
■Latch-Up Exceeds 250mA per JESD 78, Class II
■Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
■Halogen and Antimony Free. “Green” Device (Note 3)
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74HC138 、 74HC138S16 、 74HC138S16-13 、 74HC138T16 、 74HC138T16-13 、 74HC138XXX-13 |
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[ Memory chip select decoding ][ Demultiplexing ][ Single line peripheral control ][ control peripheral lines ] |
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Datasheet |
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Please see the document for details |
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SO-16;TSSOP-16 |
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English Chinese Chinese and English Japanese |
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June 2013 |
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Rev.3 - 2 |
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DS35488 |
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187 KB |
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