Using the i.MXRT L1 Cache
■i.MXRT series takes advantage of the ARM Cortex-M7 core with 32K/32K L1 I/D-Cache. This delivers extremely high performance regardless the code is executed from on-chip RAM, external Flash or external memory.
■This documentation introduces the basic technology of the cache system that includes the L1 cache, memory types, attributes and MPU (Memory Protection Unit). It guides user on how to use cache to develop applications running in a correct and high-performance way. It does not intend to dig into details of the cache system, for more detailed information, please refer to ARM Cortex-M7 Processor User Guide.
■The software used for example in this documentation are based on the i.MXRT1050 SDK release with ARM's CMSIS implementation. The development environment is IAR Embedded Workbench 8.11. The hardware used to verify the example is MIMXRT1050-EVK board.
●Overview:
■This chapter introduces i.MXRT system architecture with cache related parts. It talks about the L1 cache behavior, ARM cortex-M7 defined memory types/attributes and the MPU (Memory Protection Unit)system. This gives an overview of the i.MXRT cache system and how they affect the application use cases.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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12/2017 |
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Rev. 1 |
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AN12042 |
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706 KB |
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