Use blhost to Update LPC55(S)1x Firmware through HighSpeed USB Port
●The LPC55S1x/LPC551x is an Arm® Cortex®-M33 based microcontroller for embedded applications. These devices include CASPER Crypto engine, up to 256 KB on-chip flash, up to 96 KB of on-chip SRAM, PRINCE module for on-the-fly flash encryption/decryption, high-speed/full-speed USB host and device interface with crystal-less operation for full-speed, CAN FD, five general-purpose timers, one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), nine flexible serial communication peripherals (which can be configured as a USART, SPI, high speed SPI, I2C, or I2S interface), Programmable Logic Unit (PLU), one 16-bit 2.0 Msamples/sec ADC, comparator, and temperature sensor
●LPC55(S)1x On-chip ROM bootloader supports:
■Booting of images from on-chip flash.
■CRC32 image integrity checking.
■Flash programming through In System Programming (ISP) commands over following interfaces: USB1 interfaces using HID Class device, UART interface (Flex COMM 0) with auto baud, SPI slave interfaces (flex COMM 3 or 9) using mode 3 (CPOL = 1 and CPHA = 1), and I2C slave interface (flex COMM 1).
■ROM API functions: Flash programming API, Power control API, and Secure firmware update API using NXP Secure Boot file format, version 2.0 (SB2 files).
■Booting of images from PRINCE encrypted flash regions.
■NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1 (RSA-4096).
■Setting a sealed part to Fault Analysis mode through Debug authentication.
●This application note focuses on un-secure firmware update to LPC55(S)1x. The firmware update uses high-speed USB port (USB port 1) and cooperates with NXP open source software blhost on host computer to achieve firmware update.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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March 15, 2021 |
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Rev. 0 |
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AN13183 |
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848 KB |
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