LPC55(S)0x CoreMark Porting Guide
●CoreMark, developed by EEMBC, is a simple, yet sophisticated benchmark that is designed specifically to test the functionality of an embedded processor core. Running CoreMark produces a single-number score allowing users to make quick comparisons between processors.
●LPC55S0x/LPC550x is an Arm Cortex-M33 based microcontroller for embedded applications. These devices include:
■Up to 96 KB of on-chip SRAM, up to 256 KB on-chip flash
■Running at a frequency of up to 96 MHz
■PRINCE module for on-the-fly flash encryption/decryption
■CASPER Crypto/FFT engine
■One CAN-FD with dedicated DMA controller
■Five general-purpose timers, one SCTimer/PWM, one RTC/alarm timer
■One 24-bit Multi-Rate Timer (MRT)
■A Windowed Watchdog Timer (WWDT)
■Nine flexible serial communication peripherals (which can be configured as a USART, SPI, high speed SPI, I2C, or I2S interface)
■Programmable Logic Unit (PLU)
■One 16-bit 2.0 Msamples/sec ADC, comparator, and temperature sensor
●The Cortex-M33 offers 18.2% performance increase in the same process technology compared to the high embedded performance bars already established by Cortex-M4 processors, while improving power efficiency. Cortex-M33 official CoreMark is 4.02 CoreMark/MHz, and Cortex-M4 official CoreMark is 3.40 CoreMark/MHz.
●This application note describes how to port CoreMark code to LPC55S0x/LPC550x, which involves setting up software and hardware including memory partitioning, compiler setting, and board setup. It also describes how to measure CoreMark scores on the Cortex-M33 and the result including CoreMark scores and power consumption in μA/MHz. Separate CoreMark projects for different software development tools (Keil MDK, IAR EWARM, and MCUXpresso IDE) are also included here for reference.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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30 October 2020 |
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Rev. 0 |
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AN13035 |
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6.9 MB |
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