Timing Optimization for AXI3 DDR Interfaces Using SmartFusion2 and IGLOO2 Application Note

PublishTime：2021-07-14

This application note describes the optimization techniques used for meeting timing closure on SmartFusion®2 and IGLOO®2 designs that use non-1:1 Double Data Rate (DDR) to Advanced eXtensible Interface (AXI) clock ratios (2:1, 3:1, and 4:1). It provides reference designs for the SmartFusion2 Advanced Development Kit board and IGLOO2 Evaluation Kit board.

Brand of Product：	MICROSEMI
Part#：	IGLOO2 More Part#
Product Category：	Evaluation Kit board More
Application：	More
Data Type：	Application note & Design Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	6/21
Version Number：	Revision 2.0
Data Encoding：	AC450
Data Size：	3.2 MB

Data section preview(2pages)

- The full preview is over. If you want to read the whole 40 page document,please Sign in/Register -

Download

+1 Like
Add to Favorites

Recommend

Technical Resources

More>

All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.

Integrated Circuits