74LVC1G32 Single 2-input OR gate

2021-07-01
The 74LVC1G32 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I-OFF. The I-OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
●Features and benefits:
■Wide supply voltage range from 1.65 V to 5.5 V
■Overvoltage tolerant inputs to 5.5 V
■High noise immunity
■CMOS low power dissipation
■I-OFF circuitry provides partial Power-down mode operation
■±24 mA output drive (V-CC = 3.0 V)
■Latch-up performance exceeds 250 mA
■Direct interface with TTL levels
■Complies with JEDEC standard:
▲JESD8-7 (1.65 V to 1.95 V)
▲JESD8-5 (2.3 V to 2.7 V)
▲JESD8-B/JESD36 (2.7 V to 3.6 V)
■ESD protection:
▲HBM JESD22-A114F exceeds 2000 V
▲MM JESD22-A115-A exceeds 200 V
■Multiple package options
■Specified from -40 °C to +85 °C and -40 °C to +125 °C.

Nexperia

74LVC1G3274LVC1G32GW74LVC1G32GV74LVC1G32GM74LVC1G32GN74LVC1G32GS74LVC1G32GX74LVC1G32GF

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Part#

Single 2-input OR gate

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partial power down applications ]

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Datasheet

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Please see the document for details

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TSSOP5;SOT353-1;SC-74A;SOT753;XSON6;SOT886;SOT1115;SOT1202;X2SON5;SOT1226-3;SOT891

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18 May 2021

Rev. 13

74LVC1G32 v.13

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