74LVC3G04 Triple inverter
■The 74LVC3G04 is a triple inverter. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
■Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
■This device is fully specified for partial power down applications using I-OFF. The I-OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
●Features and benefits:
■Wide supply voltage range from 1.65 V to 5.5 V
■5 V tolerant outputs for interfacing with 5 V logic
■High noise immunity
■Complies with JEDEC standard:
▲JESD8-7 (1.65 V to 1.95 V)
▲JESD8-5 (2.3 V to 2.7 V)
▲JESD8B/JESD36 (2.7 V to 3.6 V)
■ESD protection:
▲HBM JESD22-A114F exceeds 2000 V
▲MM JESD22-A115-A exceeds 200 V
■±24 mA output drive (V-CC = 3.0 V)
■CMOS low power consumption
■Latch-up performance exceeds 250 mA
■Direct interface with TTL levels
■I-OFF circuitry provides partial Power-down mode operation
■Multiple package options
■Specified from -40 °C to +85 °C and -40 °C to +125 °C
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74LVC3G04 、 74LVC3G04DP 、 74LVC3G04DC 、 74LVC3G04GT 、 74LVC3G04GN 、 74LVC3G04GS |
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Datasheet |
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Please see the document for details |
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XSON8;SOT1203;TSSOP8;SOT505-2;VSSOP8;SOT765-1;SOT833-1;SOT1116 |
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English Chinese Chinese and English Japanese |
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16 April 2021 |
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Rev. 14 |
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74LVC3G04 |
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247 KB |
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