NB100LVEP91 2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator
■The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential LVNECL output signals (−2.5 V /−3.3 V).
■To accomplish the level translation the LVEP91 requires three power rails. The V-CC pins should be connected to the positive power supply, and the V-EE pin should be connected to the negative power supply. The GND pins are connected to the system ground plane. Both V-EE and V-CC should be bypassed to ground via 0.01 m F capacitors.
■Under open input conditions, the D input will be biased at V-CC /2 and the D input will be pulled to GND. These conditions will force the Q outputs to a low state, and Q outputs to a high state, which will ensure stability.
■The V-BB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V-BB as a switching reference voltage. V-BB may also rebias AC coupled inputs. When used, decouple V-BB and V-CC via a 0.01 m F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V-BB should be left open.
●Features:
■ Maximum Input Clock Frequency > 2.0 GHz
■ Maximum Input Data Rate > 2.0 Gb/s
■ 500 ps Propagation Delay
■ Operating Range:
◆ V-CC = 2.375 V to 3.8 V; V-EE =−2.375 V to−3.8 V; GND = 0 V
■ Q Output will Default LOW with Inputs Open or at GND
■ These Devices are Pb-Free, Halogen Free and are RoHS Compliant
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NB100LVEP91 、 NB100LVEP91MNG 、 NB100LVEP91DWR2G 、 NB100LVEP91DWG 、 NB100LVEP91MNR2G |
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Datasheet |
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Please see the document for details |
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SOIC−20 WB;QFN−24 |
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English Chinese Chinese and English Japanese |
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June, 2018 |
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Rev. 20 |
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NB100LVEP91/D |
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258 KB |
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