Micron Parallel NOR Flash Embedded Memory (P33-65nm)
The NOR Flash device provides high performance at low voltage on a 16-bit data bus.Individually erasable memory blocks are sized for optimum code and data storage.
Upon initial power up or return from reset, the device defaults to asynchronous page-mode read. Configuring the read configuration register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory PROGRAM and ERASE operations. Designed for low-volt-age systems, the devIce supports READ operations with V-CC at the low voltages, and ERASE and PROGRAM operations with VPP at the low voltages or V-PPH. Buffered enhanced factory programming (BEFP) provides the fastest Flash array programming performance with V-PP at V-PPH, which increases factory throughput. With V-PP at low voltages, V-CC and VPP can be tied together for a simple, ultra low-power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when V-PP≤ V-PPLK.
A command user interface is the interface between the system processor and all internal operations of the device. The device automatically executes the algorithms and timings necessary for block erase and program. A status register indicates ERASE or PROGRAM completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation.Each ERASE operation erases one block. The erase suspend feature enables system software to pause an ERASE cycle to read or program data in another block. Program suspend enables system software to pause programming to read other locations. Data is programmed in word increments (16 bits).
The protection register enables unique device identification that can be used to increase system security. The individual block lock feature provides zero-latency block locking and unlocking. The device includes enhanced protection via password access;this new feature supports write and/or read access protection of user-defined blocks. In addition, the device also provides the full-device OTP security feature.
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JS28F512P33BFD 、 JS28F512P33TFA 、 JS28F512P33EFA 、 PC28F512P33BFD 、 PC28F512P33TFA 、 PC28F512P33EFA 、 JS28F00AP33BFA 、 JS28F00AP33TFA 、 JS28F00AP33EFA 、 PC28F00AP33BFA 、 PC28F00AP33TFA 、 PC28F00AP33EFA 、 PC28F00BP33EFA 、 JS28F512P33EF* |
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Datasheet |
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Please see the document for details |
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TSOP;BGA |
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English Chinese Chinese and English Japanese |
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12/13 |
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Rev.C |
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09005aef845667b8 |
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2.7 MB |
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