EFM32 Gecko EFM32GG11 Errata
This document contains information on the EFM32GG11 errata. The latest available revision of this device is revision B. Several revision A part numbers are available at Engineering Status, which is denoted with revision code X. For the purposes of this document,revision “A/X” refers to both revision A and revision X part numbers.
Errata that have been resolved remain documented and can be referenced for previous revisions of this device.
The device data sheet explains how to identify the chip revision, either from package marking or electronically.
Current Errata Descriptions:
●ADC_E213 – ADC KEEPINSLOWACC Mode
●CORE_E203 – Invalid Data Cached After a Bus Fault
●CORE_E204 – SRAM Does Not Support Prefetch When ECC is Enabled
●CORE_E206 – SRAM Slave (RAM0, RAM1) Ignores the Second AHB Transaction for Back-to-Back AHB Transactions ofWhich the First AHB Transaction Caused a 2-bit ECC Related Busfault
●CSEN_E201 – CSEN_DATA in Debug Mode
●CSEN_E202 – CSEN Baseline DMA Transfers
●CUR_E203 – Occasional Extra EM0/1 Current
●CUR_E204 – Extra EM4S Current When ANASW Set to 1
●DBG_E204 – Debug Recovery with JTAG Does Not Work
●EMU_E217 — EM4S Not Supported in 5V Sub-System Powered Devices at Temperatures Above 85°C
●EMU_E220 – DECBOD Reset During Voltage Scaling After EM2 or EM3 Wakeup
●I2C_E204 – I2C0 Does Not Meet Fast Mode Plus (Fm+) Timing at Voltage Scale Level 0
●I2C_E206 – Slave Holds SCL Low After Losing Arbitration
●LES_E201 — LFPRESC Can Extend Channel Start-Up Delay
●MSC_E201 – Invalid Data Cached After a Bus Fault
●MSC_E202 – SRAM Does Not Support Prefetch When ECC is Enabled
●MSC_E204 – Second Transaction of Back-to-Back SRAM Transactions is Ignored When First Transaction Causes a 2-bit ECC Bus Fault
●RMU_E202 – External Debug Access Not Available After Watchdog or Lockup Full Reset
●TIMER_E202 — Continuous Overflow and Underflow Interrupts in Quadrature Counting Mode
●USART_E201 — USART DMA Transactions Fail with Slow Peripheral Clocks
●USART_E204 — IrDA Modulation and Transmission of PRS Input Data
●USART_E205 — Possible Data Transmission on Wrong Edge in Synchronous Mode
●WTIMER_E201 — Continuous Overflow and Underflow Interrupts in Quadrature Counting Mode
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Errata |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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April 2020 |
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Revision 0.5 |
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841 KB |
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