IDT PCI Express® Gen2 System Interconnect Switch Hardware Design Guide Application Note
●Introduction:
■This document provides system design guidelines for IDT’s PCI Express® 2.0 base specification compliant System Interconnect switch device family. Information provided in this document is applicable to the following devices: 89HPES64H16[A]G2, 89HPES48H12[A]G2, 89HPES34H16G2, 89HPES22H16G2,and 89HPES32H8G2. In this document, the PES64H16G2 is used as the primary reference. The letters“G2” within the device names indicate that these devices are capable of GEN2 (5.0 GT/S) serial data speeds. The PES64H16G2 device offers 64 PCIe lanes divided into 16 ports of 4 lanes each. The PES48H12G2 device offers 48 PCIe lanes divided into 12 ports of 4 lanes each, and so on.
■This document also describes the following device interfaces and provides relevant board design recommendations:
▲PCI Express Interface
▲Reference Clock (REFCLK) Circuitry
▲Reset (Fundamental Reset) Schemes
▲SMBus Interfaces
▲GPIO and JTAG pins
▲Power and Decoupling Scheme
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89HPES64H16G2 、 89HPES48H12G2 、 89HPES34H16G2 、 89HPES22H16G2 、 89HPES32H8G2 、 89HPES64H16AG2 、 89HPES48H12AG2 、 PES64H16G2 、 PES48H12G2 、 ICS9DB803 、 PES32H8G2 、 PCA9555 、 PCA9535 、 PCA9539 、 MAX7311 、 IOEXPADDR0 、 IOE12ADDR 、 IOE0ADDR 、 IOE2ADDR 、 IOEXPADDR3 、 PES22H16G2 、 PES34H16G2 、 PES48H12AG2 、 PES64H16AG2 |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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August 14, 2009 |
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AN-721 |
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763 KB |
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