EFR32xG21 Wireless Gecko Reference Manual
The EFR32xG21 Wireless Gecko SoC is the first device in the Series 2 Wireless GeckoPortfolio, and includes the EFR32MG21 Mighty Gecko and EFR32BG21 Blue Gecko.The EFR32xG21 improves processing capability with a Cortex M33 core and has best inclass link budget while providing for lower active current for both the MCU and radio. Thededicated security core (Secure Element) provides improved cryptography and hardwaresecurity that is isolated from the main application CPU. This high performance and se-cure multi-protocol device supports Zigbee, Thread, and Bluetooth 5.0.The single-die solution provides industry-leading energy efficiency, processing capability,and RF performance in a small form factor for IoT connected applications.
KEY FEATURES：
• 32-bit ARM® Cortex M33 core with 80 MHz maximum operating frequency
•Scalable Memory and Radio configuration options available in QFN packaging
• Peripheral Reflex System enabling autonomous interaction of MCU peripherals
• Autonomous Hardware Crypto Accelerator and True Random Number Generator
• Multiple Integrated 2.4 GHz PAs with up to 20 dBm transmit power
This document contains reference material for the EFR32xG21 devices. All modules and peripherals in the EFR32xG21 devices are described in general terms. Not all modules are present in all devices and the feature set for each device might vary. Such differences,including pinout, are covered in the device data sheets.
The high level features of EFR32xG21 include:
• High performance radio transceiver
• Low power consumption in transmit, receive, and standby modes
• Excellent receiver performance, including sensitivity, selectivity, and blocking
• Excellent transmitter performance, including
programmable output power, low phase noise, and power-amplifier (PA) ramping
• High performance, low power MCU system
• High Performance 32-bit ARM Cortex-M33 CPU
• Flexible and efficient energy management
• Complete set of digital peripherals
• Peripheral Reflex System (PRS)
• Precision analog interfaces
• Low external component count
• Fully integrated 2.4 GHz BALUN
• Integrated tunable crystal loading capacitors
• Security
• Secure Boot with Root of Trust and Secure Loader (RTSL)
• Hardware Cryptographic Acceleration with DPA countermeasures for AES128/256, SHA-1, SHA-2 (up to 256-bit), ECC (up to 256-bit), ECDSA, ECDH and J-Pake
• True Random Number Generator (TRNG) compliant with NIST SP800-90 and AIS-31
• ARM® TrustZone®
• Secure Debug with lock/unlock
A further introduction to the MCU and radio system is included in the following sections.
Note: Detailed performance numbers, current consumption, pinout etc. is available in the device datasheet.
The ARM Cortex-M33 32-bit RISC processor provides outstanding computational performance and exceptional system response to in-terrupts while meeting low cost requirements and low power consumption.The ARM Cortex-M33 implemented is revision r0p3.
Features：
•Harvard architecture
• Separate data and program memory buses (No memory bottleneck as in a single bus system)
• 3-stage pipeline
• Thumb-2 instruction set
• Enhanced levels of performance, energy efficiency, and code density
• Single cycle multiply and hardware divide instructions
• 32-bit multiplication in a single cycle
• Signed and unsigned divide operations between 2 and 12 cycles
• 1.5 DMIPS/MHz
• TrustZone
• Independent Secure and Privileged states
• Accelerated context switching
• 16 Region MPU
• 24-bit System Tick Timer for Real Time OS
• Excellent 32-bit migration choice for 8/16 bit architecture based designs
• Simplified stack-based programmer's model is compatible with traditional ARM architecture and retains the programming simplicity of legacy 8-bit and 16-bit architectures
• Aligned or unaligned data storage and access
• Contiguous storage of data requiring different byte lengths
• Data access in a single core access cycle
• Integrated power modes
• Sleep Now mode for immediate transfer to low power state
• Sleep on Exit mode for entry into low power state after the servicing of an interrupt
• Ability to extend power savings to other system components
• Optimized for low latency, nested interrupts
The EFR32xG21 contains a set of AMBA buses which move data between peripherals, memory, and the CPU. All memories and regis-ter interfaces are memory mapped into a unified address space.
The Radio Transceiver of the EFR32 Series 2 enables the user to control a wide range of settings and options for tailoring radio opera-tion precisely to the users need. It provides access to the transmit and receive data buffers and supports both dynamic and static frame lengths, as well as automatic address filtering and CRC insertion/verification.
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User's Guide |
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Please see the document for details |
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WLCSP;BGA;QFN;QFP |
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English Chinese Chinese and English Japanese |
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August, 2019 |
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Revision 0.5 |
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19.5 MB |
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