MIC68400 Evaluation Board User’s Guide
●General Description
■The MIC68400 is a high peak current LDO regulator designed specifically for powering applications such as FPGA core voltages that require high start up current with lower nominal operating current. Capable of sourcing 4A of current from start-up, the MIC68400 provides high power from a small MLF leadless package. The MIC68400 can also implement a variety of power-up and power-down protocols such as sequencing, tracking, and ratiometric tracking.
■The MIC68400 operates from a wide input range of 1.65V to 5.5V. The MIC68400 incorporates a delay pin (Delay) for control of power on reset output (POR) at turn-on and power-down delay at turn-off. In addition there is a ramp control pin (RC) for either tracking applications or output voltage slew rate adjustment at turn-on and turn-off. On board jumpers allow selection of on board delay caps, tracking, or sequencing mode.
●Features
■ Stable with 10uF ceramic capacitor
■ Input voltage range: 1.65V to 5.5V
■ Adjustable output voltage down to 0.5V
■ 4A maximum output current – peak start up
■ 3A Continuous Operating Current
■ Tracking on turn-on and turn-off
■ Timing Controlled Sequencing
■ Programmable Ramp Control™
■ Power-on Reset (POR) supervisor with programmable delay time
■ Tiny 4mm x 4mm MLFTM package
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MIC68400 、 MIC68400YML EV 、 GRM188R60J106ME47D 、 C1608X5R0J106K 、 JMK107 BJ106MA 、 08056D106KAT 、 VJ0603A102KXQPW1BC 、 VJ0603Y222KXXCW1BC 、 CRCW06031002FKEYE3 、 CRCW06030000FKEYE3 、 CRCW06034991FKEYE3 、 CRCW06033831FKEYE3 、 CRCW06032491FKEYE3 、 CRCW06031781FKEYE3 、 MIC68400YML |
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Evaluation Board User's Manual |
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Please see the document for details |
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MLF |
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English Chinese Chinese and English Japanese |
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December 2005 |
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M9999-120105 |
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569 KB |
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